Invited Talks

Conference Speakers

Avi Mendelson, visiting professor at the CS and EE departments at the Technion and in the EEE department, NTU Singapore

Static vs. Dynamic Hardware Security Protection Mechanisms

Abstract: As numbers of transistors on a single die increases in an exponential pace, the complexity of systems increases accordingly and so, it makes systems to be vulnerable to errors, incomplete specifications, and other cyber-related attacks. It seems that the overall complexity of modern systems reaches the point that it is near to impossible to truly test and verify the correctness of all the possible usage models and execution paths. Thus, this presentation will claim that static protection on the system is not feasible anymore and a new approach is needed.
In my talk, I will claim that more dynamic approach is needed in order to protect such complex systems and presents new ideas which are motivated by fault tolerance and systems’ testing techniques.

Avi Mendelson is an IEEE Fellow and a second VP of the IEEE Computer Society. He is a visiting professor at the CS and EE departments at the Technion and in the EEE department, NTU Singapore. He has a blend of industrial and academic experience in several different areas such as Computer architecture, Power management, security and Real-Time systems. Prof. Mendelson published more than 130 papers in refereed Journals conferences and workshops and holds more than 25 Patents. Among his industrial roles, he worked for National semiconductors, Intel and Microsoft.

Benoît Dupont de Dinechin, CTO Kalray, France

Kalrays MPPA^® Manycore Processor: At the Heart of Intelligent Systems

Abstract: Intelligent systems can be defined as cyber-physical systems with integration of high-integrity functions, such as control-command, along with high- performance functions, in particular signal processing, image processing and machine learning. Such intelligent systems are required by defense and aerospace applications, and by automated vehicles.
The Kalray MPPA3 manycore processor is designed as a building block for such intelligent systems. Its architecture comprises multiple compute units connected by on-chip global fabrics to external memory systems and network interfaces. Selecting compute units assembled from fully programmable cores, a large local memory and an asynchronous data transfer engine enables to match the high performance and energy efficiency of GPGPU processors, while avoiding their limitations.
For the high-performance functions, we illustrate how the MPPA3 processor accelerates deep learning inference by distributing computations across compute units and cores, and by offloading tensor operations to the tightly coupled co-processor connected to each core. For the high-integrity functions, we present a model-based systems engineering approach based on multicore code generation from the synchronous-reactive language SCADE Suite from Ansys.

BenoîĚ‚t Dupont de Dinechin is the Chief Technology Officer of Kalray. He is the Kalray VLIW core main architect, and the co-architect of the Multi-Purpose Processing Array (MPPA) processor. BenoîĚ‚t also defined the Kalray software roadmap and contributed to its implementation. Before joining Kalray, BenoîĚ‚t was in charge of Research and Development of the STMicroelectronics Software, Tools, Services division, and was promoted to STMicroelectronics Fellow in 2008. Prior to STMicroelectronics, Benoı̂t worked at the Cray Research park (Minnesota, USA), where he developed the software pipeliner of the Cray T3E production compilers. BenoîĚ‚t earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Suprieure de l’Aronautique et de l’Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill University (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao.
Benoı̂t authored 14 patents in the area of computer architecture, and published over 55 conference papers, journal articles and book chapters in the areas of parallel computing, compiler design and operations research.

Wolfgang Schröder-Preikschat, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany

Predictability Issues in Operating Systems

Abstract: Predictability is always subject to the underlying assumptions being made. For real-time systems, time response of processes in relation to the strictness of deadlines is of particular importance. With an additional focus on embedded systems, space and energy requirements become relevant as well and need to be considered in combination. As far as software is concerned, structure and organisation of the programs to be executed determines whether or not predictable processes will take place in a given computing system. Design for predictability is an overarching aspect that crosscuts the whole computing system and particularly addresses operating systems.
This talk is about structuring principles of non-sequential programs - in the shape of but not limited to operating systems - to abet predetermination of quality attributes of non-sequential (real-time) processes, it is not about analytical methods to effectively predetermine these attributes. Issues in operating systems as to space, timing, and energy requirement are touched. Emphasis thereby is on coordination of cooperation and competition between processes, namely synchronisation. It is shown how measures of process synchronisation against the background of many-core processors cater to these issues.

Dr. Wolfgang Schröder-Preikschat studied computer science at the Technical University of Berlin, Germany, where he also received his doctoral degree and venia legendi. After a decade of extra-university research at the German National Research Center of Computer Science (GMD), Research Institute for Computer Architecture and Software Technique (FIRST), Berlin, he became a full professor for computer science at the Universities of Potsdam, Magdeburg, and Erlangen-Nuremberg (FAU), Germany. He is elected member of the DFG (German Research Foundation) Review Board on subject area Operating, Communication, Database and Distributed Systems, his main research interests are in the domain of real-time embedded distributed/parallel operating systems. He is member of ACM, EuroSys, GI/ITG, IEEE, and USENIX.